The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Aug. 13, 2010
Applicants:

Amitabh Jain, Allen, TX (US);

Deborah J. Riley, Murphy, TX (US);

Inventors:

Amitabh Jain, Allen, TX (US);

Deborah J. Riley, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 29/7848 (2013.01); H01L 21/823807 (2013.01);
Abstract

An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.


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