The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2014
Filed:
Jun. 22, 2011
Applicant:
George R. Leal, Cedar Park, TX (US);
Inventor:
George R. Leal, Cedar Park, TX (US);
Assignee:
Freescale Semiconductor, Inc., Austin, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/544 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/56 (2013.01); H01L 23/544 (2013.01); H01L 21/6836 (2013.01); H01L 23/3128 (2013.01); H01L 2224/12105 (2013.01); H01L 24/19 (2013.01); H01L 21/6835 (2013.01); H01L 2223/54426 (2013.01); H01L 23/3135 (2013.01); H01L 24/20 (2013.01); H01L 25/0655 (2013.01); H01L 2221/6834 (2013.01); H01L 2223/5442 (2013.01); H01L 2224/19 (2013.01); H01L 2924/00013 (2013.01); H01L 24/24 (2013.01); H01L 2224/24137 (2013.01); H01L 2221/68327 (2013.01); H01L 2223/54473 (2013.01); H01L 2224/20 (2013.01); H01L 21/561 (2013.01);
Abstract
A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.