The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2014
Filed:
Mar. 27, 2008
Bang-chiang Lan, Taipei, TW;
Li-hsun Ho, Hsinchu County, TW;
Wei-cheng Wu, Hsinchu County, TW;
Hui-min Wu, Changhua County, TW;
Min Chen, Taipei County, TW;
Tzung-i Su, Yun-Lin County, TW;
Chien-hsin Huang, Taichung, TW;
Bang-Chiang Lan, Taipei, TW;
Li-Hsun Ho, Hsinchu County, TW;
Wei-Cheng Wu, Hsinchu County, TW;
Hui-Min Wu, Changhua County, TW;
Min Chen, Taipei County, TW;
Tzung-I Su, Yun-Lin County, TW;
Chien-Hsin Huang, Taichung, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping element is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping element has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.