The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Jun. 25, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki, JP;

Inventors:

Takehiro Ueda, Kawasaki, JP;

Hiroshi Kawaguchi, Kawasaki, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 29/66795 (2013.01); H01L 29/4236 (2013.01); H01L 29/665 (2013.01); H01L 29/7851 (2013.01); H01L 29/4238 (2013.01);
Abstract

A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.


Find Patent Forward Citations

Ueda, Takehiro. (2014). Method of manufacturing a semiconductor device including concave portion (U.S. Patent No. 8871592). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8871592

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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