The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Dec. 20, 2010
Applicants:

George A. Dunbar, Iii, Essex Junction, VT (US);

Zhong-xiang He, Essex Junction, VT (US);

Jeffrey C. Maling, Grand Isle, VT (US);

William J. Murphy, North Ferrisburgh, VT (US);

Anthony K. Stamper, Williston, VT (US);

Inventors:

George A. Dunbar, III, Essex Junction, VT (US);

Zhong-Xiang He, Essex Junction, VT (US);

Jeffrey C. Maling, Grand Isle, VT (US);

William J. Murphy, North Ferrisburgh, VT (US);

Anthony K. Stamper, Williston, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); B81C 1/00 (2006.01); B81B 3/00 (2006.01); G06F 17/50 (2006.01); H01H 57/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0021 (2013.01); B81C 1/00476 (2013.01); B81C 2201/0167 (2013.01); G06F 17/5072 (2013.01); B81C 2201/017 (2013.01); B81B 2201/014 (2013.01); H01H 57/00 (2013.01); B81C 2201/0109 (2013.01); H01H 2057/006 (2013.01); B81B 2203/04 (2013.01); B81B 2203/0118 (2013.01); Y10S 438/937 (2013.01);
Abstract

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.


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