The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Jan. 06, 2012
Derick Gardner Behrends, Rochester, MN (US);
Todd Alan Christensen, Rochester, MN (US);
Travis Reynold Hebig, Rochester, MN (US);
Michael Launsbach, Rochester, MN (US);
Daniel Mark Nelson, Rochester, MN (US);
Derick Gardner Behrends, Rochester, MN (US);
Todd Alan Christensen, Rochester, MN (US);
Travis Reynold Hebig, Rochester, MN (US);
Michael Launsbach, Rochester, MN (US);
Daniel Mark Nelson, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.