The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Jun. 29, 2007
Applicants:

Mahalingam Nandakumar, Richardson, TX (US);

Wayne Bather, Richardson, TX (US);

Narendra Singh Mehta, Dallas, TX (US);

Inventors:

Mahalingam Nandakumar, Richardson, TX (US);

Wayne Bather, Richardson, TX (US);

Narendra Singh Mehta, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/3115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7847 (2013.01); H01L 21/823807 (2013.01); H01L 29/6659 (2013.01); H01L 21/823814 (2013.01); H01L 21/8238 (2013.01); H01L 21/31155 (2013.01);
Abstract

A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.


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