The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Dec. 24, 2013
Renesas Electronics Corporation, Kodaira, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate () in a low-voltage NMOS region (LNR) thereby to form extension layers (). Then, a silicon oxide film (OX) is formed to cover the whole surface of the silicon substrate (). The silicon oxide film (OX) on the side surfaces of gate electrodes (-) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate () in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers () later to be extension layers ().