The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Feb. 16, 2011
Applicants:

Shinnosuke Maeda, Nagoya, JP;

Tetsuo Suzuki, Niwa-gun, JP;

Satoshi Hirano, Chita-gun, JP;

Inventors:

Shinnosuke Maeda, Nagoya, JP;

Tetsuo Suzuki, Niwa-gun, JP;

Satoshi Hirano, Chita-gun, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B32B 3/24 (2006.01); H05K 3/46 (2006.01); H05K 1/11 (2006.01); H05K 3/20 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4682 (2013.01); H05K 2201/099 (2013.01); H05K 1/112 (2013.01); H05K 3/205 (2013.01); H05K 2201/09472 (2013.01); H05K 2201/094 (2013.01);
Abstract

A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.


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