The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Feb. 24, 2009
Applicants:

Erich R. Klawuhn, Los Altos, CA (US);

Robert Rozbicki, San Francisco, CA (US);

Girish A. Dixit, San Jose, CA (US);

Inventors:

Erich R. Klawuhn, Los Altos, CA (US);

Robert Rozbicki, San Francisco, CA (US);

Girish A. Dixit, San Jose, CA (US);

Assignee:

Novellus Systems, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 14/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.


Find Patent Forward Citations

Loading…