The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8856720 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 07, 2014

Filed:

Jan. 03, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Steven M. Douskey, Rochester, MN (US);

Ryan A. Fitch, Southfield, MI (US);

Michael J. Hamilton, Rochester, MN (US);

Amanda R. Kaufer, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/50 (2013.01);
Abstract

A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.


Find Patent Forward Citations

Douskey, Steven. (2014). Test coverage of integrated circuits with masking pattern selection (U.S. Patent No. 8856720). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8856720

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…