The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Jun. 29, 2006
Xiangdong Chen, Poughquag, NY (US);
Thomas W. Dyer, Pleasant Valley, NY (US);
Kenneth Settlemyer, Bradenton, FL (US);
Haining S. Yang, Wappingers Falls, NY (US);
Xiangdong Chen, Poughquag, NY (US);
Thomas W. Dyer, Pleasant Valley, NY (US);
Kenneth Settlemyer, Bradenton, FL (US);
Haining S. Yang, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.