The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Jan. 12, 2010
Applicants:

Justin H. Sato, West Linn, OR (US);

Brian Hennes, Portland, OR (US);

Greg Stom, Damascus, OR (US);

Robert P. MA, Phoenix, AZ (US);

Walter E. Lundy, Gilbert, AZ (US);

Inventors:

Justin H. Sato, West Linn, OR (US);

Brian Hennes, Portland, OR (US);

Greg Stom, Damascus, OR (US);

Robert P. Ma, Phoenix, AZ (US);

Walter E. Lundy, Gilbert, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76229 (2013.01); H01L 21/3083 (2013.01);
Abstract

A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.


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