The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2014
Filed:
Nov. 18, 2010
Xiying Chen Costa, San Jose, CA (US);
Roy Scheuerlein, Cupertino, CA (US);
Abhijit Bandyopadhyay, San Jose, CA (US);
Brian Le, San Jose, CA (US);
LI Xiao, San Jose, CA (US);
Tao Du, Palo Alto, CA (US);
Chandrasekhar R. Gorla, Sunnyvale, CA (US);
Xiying Chen Costa, San Jose, CA (US);
Roy Scheuerlein, Cupertino, CA (US);
Abhijit Bandyopadhyay, San Jose, CA (US);
Brian Le, San Jose, CA (US);
Li Xiao, San Jose, CA (US);
Tao Du, Palo Alto, CA (US);
Chandrasekhar R. Gorla, Sunnyvale, CA (US);
SanDisk 3D LLC, Milpitas, CA (US);
Abstract
A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.