The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Apr. 19, 2012
Applicants:

Hiroshi Tomotani, Osaka, JP;

Kazuhiko Shimakawa, Osaka, JP;

Yuichiro Ikeda, Hyogo, JP;

Inventors:

Hiroshi Tomotani, Osaka, JP;

Kazuhiko Shimakawa, Osaka, JP;

Yuichiro Ikeda, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 2029/5006 (2013.01); G11C 29/50 (2013.01); G11C 13/0007 (2013.01); G11C 2213/72 (2013.01); G11C 13/004 (2013.01);
Abstract

A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.


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