The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2014
Filed:
Jun. 25, 2013
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 27/105 (2006.01); H01L 29/78 (2006.01); H01L 21/225 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7831 (2013.01); H01L 21/823821 (2013.01); H01L 21/28035 (2013.01); H01L 27/105 (2013.01); H01L 29/7851 (2013.01); H01L 27/1052 (2013.01); H01L 21/82385 (2013.01); H01L 29/66795 (2013.01); H01L 21/823842 (2013.01); H01L 29/66621 (2013.01); H01L 21/2256 (2013.01);
Abstract
A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.