The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8846462 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 30, 2014

Filed:

Oct. 28, 2011
Applicants:

Martin Ostermayr, Beacon, NY (US);

Chandrasekhar Sarma, Poughkeepsie, NY (US);

Inventors:

Martin Ostermayr, Beacon, NY (US);

Chandrasekhar Sarma, Poughkeepsie, NY (US);

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 29/6659 (2013.01);
Abstract

A system and a method for transistor level routing are disclosed. The method comprises forming a high-k dielectric layer over a substrate, forming a metal layer directly over the high-k dielectric layer, and selectively disposing a semiconductive layer over the metal layer. The method further comprises forming a first transistor in a first region and a second transistor in a second region spaced from the first region, the first and second transistor having gate stacks comprising a high-k dielectric layer, a metal layer and a semiconductive layer, and forming an electrical connection between the first transistor and the second transistor comprising the high-k dielectric layer and the metal layer but not the semiconductive layer.


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