The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2014
Filed:
Sep. 24, 2012
Christopher J. Nelson, Gilbert, AZ (US);
Tak M. Mak, Union City, CA (US);
David J. Zimmerman, El Dorado Hills, CA (US);
Pete D. Vogt, Boulder, CO (US);
Christopher J. Nelson, Gilbert, AZ (US);
Tak M. Mak, Union City, CA (US);
David J. Zimmerman, El Dorado Hills, CA (US);
Pete D. Vogt, Boulder, CO (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.