The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Sep. 24, 2010
Glenn Hinton, Portland, OR (US);
Madhavan Parthasarathy, Portland, OR (US);
Rajesh Parthasarathy, Hillsboro, OR (US);
Muthukumar Swaminathan, Folsom, CA (US);
Raj Ramanujan, Federal Way, WA (US);
David Zimmerman, El Dorado Hills, CA (US);
Larry O. Smith, Beaverton, OR (US);
Adrian C. Moga, Portland, OR (US);
Scott J. Cape, Portland, OR (US);
Wayne A. Downer, Portland, OR (US);
Robert S. Chappell, Portland, OR (US);
Glenn Hinton, Portland, OR (US);
Madhavan Parthasarathy, Portland, OR (US);
Rajesh Parthasarathy, Hillsboro, OR (US);
Muthukumar Swaminathan, Folsom, CA (US);
Raj Ramanujan, Federal Way, WA (US);
David Zimmerman, El Dorado Hills, CA (US);
Larry O. Smith, Beaverton, OR (US);
Adrian C. Moga, Portland, OR (US);
Scott J. Cape, Portland, OR (US);
Wayne A. Downer, Portland, OR (US);
Robert S. Chappell, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.