The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Aug. 12, 2011
Applicants:

Yu Hwan RO, Seongnam-si, KR;

Beak Hyung Cho, Hwaseong-si, KR;

Ki Whan Song, Yongin-si, KR;

Young Don Choi, Seoul, KR;

Inventors:

Yu Hwan Ro, Seongnam-si, KR;

Beak Hyung Cho, Hwaseong-si, KR;

Ki Whan Song, Yongin-si, KR;

Young Don Choi, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4094 (2006.01); G11C 7/02 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 7/02 (2013.01); G11C 7/1048 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 11/4097 (2013.01);
Abstract

A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.


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