The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Dec. 27, 2012
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byung-Kwan You, Seoul, KR;

Seung-Woo Paek, Yongin-si, KR;

Chung-Il Hyun, Seoul, KR;

Jung-Dal Choi, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 27/10 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10 (2013.01); H01L 27/11524 (2013.01); H01L 29/66636 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/115 (2013.01);
Abstract

A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns.


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