The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Jun. 18, 2012
Che Ta Hsu, San Jose, CA (US);
Fangyun Richter, San Jose, CA (US);
Ning Cheng, San Jose, CA (US);
Jeffrey Xiaoqi Tung, Palo Alto, CA (US);
Che Ta Hsu, San Jose, CA (US);
Fangyun Richter, San Jose, CA (US);
Ning Cheng, San Jose, CA (US);
Jeffrey Xiaoqi Tung, Palo Alto, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.