The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Feb. 21, 2007
Applicants:
Johan Weijtmans, Richardson, TX (US);
Jiong-ping LU, Overijse, BE;
Rick Wise, Fairview, TX (US);
Inventors:
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7834 (2013.01); H01L 29/6656 (2013.01); H01L 29/7848 (2013.01); H01L 21/823814 (2013.01); H01L 29/66636 (2013.01); H01L 21/823807 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/165 (2013.01);
Abstract
A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.