The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Feb. 21, 2012
Applicant:
Fumitake Mieno, Beijing, CN;
Inventor:
Fumitake Mieno, Beijing, CN;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/335 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28194 (2013.01); H01L 21/02181 (2013.01); H01L 29/518 (2013.01); H01L 29/66553 (2013.01); H01L 21/02282 (2013.01); H01L 29/4983 (2013.01); H01L 21/02307 (2013.01); H01L 29/66545 (2013.01); H01L 21/0228 (2013.01); H01L 21/3105 (2013.01); H01L 21/02123 (2013.01);
Abstract
A semiconductor device includes a substrate having an active region, a gate structure on the active region, and spacers formed on opposite sides of the gate structure. The gate structure includes a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and sidewalls on both side surfaces of the gate structure. Each of the sidewalls is interposed between the metal gate and one of the spacers. The sidewalls include a self-assembly material. The gate dielectric layer includes a high-K material. The spacers include silicon nitride. The gate structure also includes a buffer layer interposed between the metal gate and the gate dielectric layer.