The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Mar. 28, 2013
Taiwan Semiconductor Manfacturing Company Limited, Hsin-Chu, TW;
Min-Shueh Yuan, Taipei, TW;
Chao-Chieh Li, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Abstract
Among other things, one or more techniques and systems for generating a common design rule check (DRC) rule set for verification of a design layout and for generating a common dummy insertion utility for design layout processing are provided. That is, the common DRC rule set comprises a set of design rules having design rule constraint values corresponding to a restriction threshold, such as a most restrictive value. The common dummy insertion utility is used to insert dummy polygons into a design layout according to a dummy size constraint and a dummy spacing constraint. The design layout is verified as compliant with the common DRC rule set. Once verified, the design layout can be converted from a universal design layout format to a target metal scheme to create a transformed design layout. In this way, design layouts, formatted according to the universal design layout, can be transformed to other formats.