The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Sep. 25, 2008
Applicants:

Bhyrav M Mutnury, Austin, TX (US);

Moises Cases, Austin, TX (US);

Nanju NA, Essex Junction, VT (US);

Tae Hong Kim, Austin, TX (US);

Inventors:

Bhyrav M Mutnury, Austin, TX (US);

Moises Cases, Austin, TX (US);

Nanju Na, Essex Junction, VT (US);

Tae Hong Kim, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 1/16 (2006.01); H05K 3/24 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0231 (2013.01); H05K 1/162 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/48227 (2013.01); H05K 2203/049 (2013.01); H05K 3/242 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.


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