The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Nov. 05, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, KR;

Inventors:

Jae-Hwang Sim, Seoul, KR;

Keon-Soo Kim, Hwaseong-si, KR;

Kyung-Hoon Min, Seoul, KR;

Min-Sung Song, Hwaseong-si, KR;

Yeon-Wook Jung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 29/7881 (2013.01); H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 29/66825 (2013.01);
Abstract

In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.


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