The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8828839 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 09, 2014

Filed:

Jan. 29, 2013
Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

David P. Brunco, Tervuren, BE;

Witold Maszara, Morgan Hill, CA (US);

Assignee:

GLOBALFOUNDRIES, Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/762 (2013.01); Y10S 438/947 (2013.01); Y10S 438/942 (2013.01);
Abstract

Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces.


Find Patent Forward Citations

Brunco, David. (2014). Methods for fabricating electrically-isolated finfet semiconductor devices (U.S. Patent No. 8828839). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8828839

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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