The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Sep. 19, 2013
Texas Instruments Incorporated, Dallas, TX (US);
James Walter Blatchford, Saratoga Springs, NY (US);
Chet Vernon Lenox, Venus, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming PMOS transistors. A SiGe cavity formation process includes cavity etching a structure including a gate stack having a gate electrode on a gate dielectric on a substrate, a sidewall spacer, and a hardmask layer on the gate electrode. The cavity etching includes (i) a first anisotropic dry etch for etching through the hardmask layer lateral to the gate stack and beginning a recessed cavity in the substrate, (ii) a dry lateral etch, and (iii) a second anisotropic dry etch. A wet crystallographic etch completes formation of the recessed cavity. A customized time is calculated for a selected dry etch step from the plurality of dry etch steps based on in-process SiGe cavity data for a measured cavity parameter for a SiGe cavity formation process. The customized time for the selected dry etch is used to cavity etch at least one substrate in a lot or run.