The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Nov. 01, 2011
Applicants:

Sung Su Park, Seoul, KR;

Kyung Han Ryu, Kyunggi-do, KR;

Sang Mok Lee, Seoul, KR;

Inventors:

Sung Su Park, Seoul, KR;

Kyung Han Ryu, Kyunggi-do, KR;

Sang Mok Lee, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/98 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.


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