The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2014
Filed:
May. 09, 2013
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Wen-Yao Hsieh, Sanchong, TW;
Che-Yu Chiu, Hsin-Chu, TW;
Anwei Peng, Hsin-Chu, TW;
Jian-Hung Chen, Shulin, TW;
Hsueh-Chen Wu, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2011.01); G05B 19/02 (2006.01); G03F 7/20 (2006.01); G05B 19/418 (2006.01); G05B 19/402 (2006.01);
U.S. Cl.
CPC ...
G05B 19/02 (2013.01); G03F 7/70458 (2013.01); G05B 2219/45031 (2013.01); G05B 19/41885 (2013.01); G05B 19/402 (2013.01); Y10S 438/975 (2013.01);
Abstract
A method for aligning a photolithographic machine in an automated semiconductor manufacturing system is provided. The method may include identifying a maximum precision degree for a wafer and identifying a maximum overlay correction value. The method may simulate one or more algorithms to determine whether an algorithm aligns a leading lot within alignment specifications. The method may align a photolithography machine using an algorithm selected based on the simulations.