The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2014
Filed:
Dec. 07, 2011
Hyo-jung Kim, Seoul, KR;
Ki-hyun Hwang, Seongnam-si, KR;
Kyung-hyun Kim, Seoul, KR;
Han-mei Choi, Seoul, KR;
Dong-chul Yoo, Seongnam-si, KR;
Chan-jin Park, Yongin-si, KR;
Jong-heun Lim, Seoul, KR;
Myung-jung Pyo, Hwaseong-si, KR;
Byoung-moon Yoon, Suwon-si, KR;
Chang-sup Mun, Suwon-si, KR;
Hyo-Jung Kim, Seoul, KR;
Ki-hyun Hwang, Seongnam-si, KR;
Kyung-Hyun Kim, Seoul, KR;
Han-Mei Choi, Seoul, KR;
Dong-Chul Yoo, Seongnam-si, KR;
Chan-Jin Park, Yongin-si, KR;
Jong-Heun Lim, Seoul, KR;
Myung-Jung Pyo, Hwaseong-si, KR;
Byoung-Moon Yoon, Suwon-si, KR;
Chang-Sup Mun, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.