The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2014
Filed:
Nov. 09, 2009
Ka-kei Kwok, Saratoga, CA (US);
Priya Viswanathan, Santa Clara, CA (US);
Rojer Raji Sabbagh, Ottawa, CA;
Ramesh Sathianathan, Sunnyvale, CA (US);
Ka-Kei Kwok, Saratoga, CA (US);
Priya Viswanathan, Santa Clara, CA (US);
Rojer Raji Sabbagh, Ottawa, CA;
Ramesh Sathianathan, Sunnyvale, CA (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation. Furthermore, in various implementations, the specific clock domain crossing verification checks employed during block level verification and top level verification are specified by a user of the implementation.