The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2014
Filed:
Sep. 28, 2009
Applicants:
Noriyuki Matsui, Kawasaki, JP;
Hidehisa Sakai, Kawasaki, JP;
Inventors:
Noriyuki Matsui, Kawasaki, JP;
Hidehisa Sakai, Kawasaki, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/498 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/3677 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 2924/15311 (2013.01);
Abstract
A semiconductor apparatus including: a substrate; and a semiconductor chip mounted on the substrate, wherein the substrate has plural holes, and the plural holes are provided such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.
Matsui, Noriyuki. (2014). Semiconductor apparatus, substrate design method, and substrate design apparatus (U.S. Patent No. 8816510). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8816510
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile