The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2014

Filed:

Nov. 08, 2013
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Ki-Hong Lee, Icheon-si, KR;

Kwon Hong, Icheon-si, KR;

Assignee:

SK Hynix Inc., Icheon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 29/7881 (2013.01); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01);
Abstract

A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.


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