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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8816411 B1

PDFFull Text
Date of Patent:
Aug. 26, 2014

Filed:

May. 31, 2013

Mosfet package

Applicants:

Renesas Electronics Corporation, Kawasaki, JP;

Renesas Eastern Japan Semiconductor, Inc., Tokyo, JP;

Inventors:

Ryoichi Kajiwara, Hitachi, JP;

Masahiro Koizumi, Hitachi, JP;

Toshiak Morita, Hitachi, JP;

Kazuya Takahashi, Hitachinaka, JP;

Munehisa Kishimoto, Kamakura, JP;

Shigeru Ishii, Tomiya-machi, JP;

Toshinori Hirashima, Takasaki, JP;

Yasushi Takahashi, Takasaki-chi, JP;

Toshiyuki Hata, Maebashi, JP;

Hiroshi Sato, Takasaki, JP;

Keiichi Ookawa, Takasaki, JP;

Assignees:

Renesas Electronics Corporation, Kanagawa, JP;

Renesas Eastern Japan Semiconductor, Inc., Tokyo, JP;

Attorney:

Antonelli, Terry, Stout & Kraus, LLP.

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01R 9/00 (2006.01); H01L 21/00 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H05K 3/34 (2006.01); H01L 21/56 (2006.01); H01L 29/78 (2006.01); H01L 23/28 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49555 (2013.01); H01L 23/3107 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 21/4814 (2013.01); H05K 3/3426 (2013.01); H01L 21/56 (2013.01); H01L 29/7833 (2013.01); H01L 23/28 (2013.01); H01L 23/4952 (2013.01);
Abstract

A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.

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