The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2014

Filed:

Nov. 08, 2012
Applicants:

Sang-ryol Yang, Gyeonggi-do, KR;

Yoo-chul Kong, Seoul, KR;

Jung-ho Kim, Gyeonggi-do, KR;

Jin-gyun Kim, Gyeonggi-do, KR;

Jae-jin Shin, Seoul, KR;

Ji-hoon Choi, Gyeonggi-do, KR;

Inventors:

Sang-Ryol Yang, Gyeonggi-do, KR;

Yoo-Chul Kong, Seoul, KR;

Jung-Ho Kim, Gyeonggi-do, KR;

Jin-Gyun Kim, Gyeonggi-do, KR;

Jae-Jin Shin, Seoul, KR;

Ji-Hoon Choi, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.


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