The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Apr. 29, 2013
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Sarvesh Bhardwaj, Fremont, CA (US);

Khalid Rahmat, Fremont, CA (US);

Kayhan Kucukcakar, Los Altos, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.


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