The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
Dec. 30, 2009
Huajun Wen, Austin, TX (US);
Joshua D. Friedrich, Round Rock, TX (US);
Norman K. James, Liberty Hill, TX (US);
Seongwon Kim, Old Tappan, NJ (US);
John R. Ripley, Austin, TX (US);
Edmund J. Sprogis, Williston, VT (US);
Huajun Wen, Austin, TX (US);
Joshua D. Friedrich, Round Rock, TX (US);
Norman K. James, Liberty Hill, TX (US);
Seongwon Kim, Old Tappan, NJ (US);
John R. Ripley, Austin, TX (US);
Edmund J. Sprogis, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.