The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Jun. 26, 2009
Applicants:

Jan Gray, Bellevue, WA (US);

David Callahan, Seattle, WA (US);

Burton Jordan Smith, Seattle, WA (US);

Gad Sheaffer, Haifa, IL;

Ali-reza Adl-tabatabai, San Jose, CA (US);

Inventors:

Jan Gray, Bellevue, WA (US);

David Callahan, Seattle, WA (US);

Burton Jordan Smith, Seattle, WA (US);

Gad Sheaffer, Haifa, IL;

Ali-Reza Adl-Tabatabai, San Jose, CA (US);

Assignee:

Microsoft Corporation, Redmond, WA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions.


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