The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

May. 09, 2013
Applicants:

Eric Yang, Saratoga, CA (US);

Jinghai Zhou, San Jose, CA (US);

Hunt Hang Jiang, San Jose, CA (US);

Inventors:

Eric Yang, Saratoga, CA (US);

Jinghai Zhou, San Jose, CA (US);

Hunt Hang Jiang, San Jose, CA (US);

Assignee:

Monolithic Power Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 24/48 (2013.01); H01L 2225/06558 (2013.01); H01L 2924/13091 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/48247 (2013.01); H01L 25/0652 (2013.01); H01L 2224/85439 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01);
Abstract

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.


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