The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
Jan. 25, 2011
Kentaro Mori, Minato-ku, JP;
Shintaro Yamamichi, Minato-ku, JP;
Hideya Murai, Minato-ku, JP;
Katsumi Kikuchi, Minato-ku, JP;
Yoshiki Nakashima, Minato-ku, JP;
Daisuke Ohshima, Minato-ku, JP;
Kentaro Mori, Minato-ku, JP;
Shintaro Yamamichi, Minato-ku, JP;
Hideya Murai, Minato-ku, JP;
Katsumi Kikuchi, Minato-ku, JP;
Yoshiki Nakashima, Minato-ku, JP;
Daisuke Ohshima, Minato-ku, JP;
NEC Corporation, Tokyo, JP;
Abstract
A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.