The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Jul. 12, 2010
Applicants:

Guan-de Lee, Hsinchu, TW;

Chien-hung Liu, Hsinchu, TW;

Shou-wei Huang, Hsinchu, TW;

Ying-tso Chen, Hsinchu, TW;

Inventors:

Guan-De Lee, Hsinchu, TW;

Chien-Hung Liu, Hsinchu, TW;

Shou-Wei Huang, Hsinchu, TW;

Ying-Tso Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 21/74 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/743 (2013.01);
Abstract

A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.


Find Patent Forward Citations

Loading…