The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
Sep. 29, 2011
Wilbur Luo, San Jose, CA (US);
Olivier Pribetich, Vallauris, FR;
Olivier Omedes, Roquefort les Pins, FR;
Roland Ruehl, San Carlos, CA (US);
Ya-chieh Lai, Mountain View, CA (US);
Frank E. Gennari, San Jose, CA (US);
Wilbur Luo, San Jose, CA (US);
Olivier Pribetich, Vallauris, FR;
Olivier Omedes, Roquefort les Pins, FR;
Roland Ruehl, San Carlos, CA (US);
Ya-Chieh Lai, Mountain View, CA (US);
Frank E. Gennari, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.