The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2014
Filed:
Oct. 31, 2012
Cadence Design Systems, Inc., San Jose, CA (US);
Regis Colwell, Gibsonia, PA (US);
Arnold Ginetti, Antibes, FR;
Khalid ElGalaind, Allison Park, PA (US);
Thomas Jordan, Pittsburgh, PA (US);
Jose A. Martinez, Pittsburgh, PA (US);
Jeffrey Markham, San Jose, CA (US);
Steven Riley, San Jose, CA (US);
Chung-Do Yang, Saratoga, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.