The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Feb. 14, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, KR;

Inventors:

Ki Ho Chung, Suwon-si, KR;

Sang-Soo Park, Hwaseong-si, KR;

Ji-Suk Kim, Seoul, KR;

Doo-Ho Cho, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 2211/5621 (2013.01); G11C 16/0483 (2013.01); G11C 16/3459 (2013.01); G01C 2213/71 (2013.01);
Abstract

A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state.


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