The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Apr. 09, 2007
Ramesh Kumar Illikkal, Portland, OR (US);
Ravishankar Iyer, Portland, OR (US);
Jaideep Moses, Portland, OR (US);
Don Newell, Portland, OR (US);
Tryggve Fossum, Northborough, MA (US);
Ramesh Kumar Illikkal, Portland, OR (US);
Ravishankar Iyer, Portland, OR (US);
Jaideep Moses, Portland, OR (US);
Don Newell, Portland, OR (US);
Tryggve Fossum, Northborough, MA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.