The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

Jan. 10, 2013
Applicant:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Inventors:

Vinh Ho, Milpitas, CA (US);

Magathi Jayaram, San Jose, CA (US);

Allan Lin, Cupertino, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01);
Abstract

In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.


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