The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

May. 24, 2011
Applicants:

Michael L. Rutigliano, Chandler, AZ (US);

Eric J. M. Moret, Beaverton, OR (US);

David Shia, Hillsboro, OR (US);

Inventors:

Michael L. Rutigliano, Chandler, AZ (US);

Eric J. M. Moret, Beaverton, OR (US);

David Shia, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 1/073 (2006.01);
U.S. Cl.
CPC ...
G01R 1/0735 (2013.01);
Abstract

Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.


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