The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Aug. 05, 2011
Hiroaki Tomita, Ota, JP;
Kazuyuki Suto, Ashikaga, JP;
Hiroaki Tomita, Ota, JP;
Kazuyuki Suto, Ashikaga, JP;
Semiconductor Components Industries, LLC, Phoenix, AZ (US);
Abstract
In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center. A second wiring is then formed so as to be connected to the first wiring exposed in the window and extend onto the back surface of the semiconductor substrate over the step portions of the window except part of the step portions on the dicing line and near the dicing line, which extend perpendicular to the dicing line.